/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
 */

#ifndef _IRQ_GIC_COMMON_H
#define _IRQ_GIC_COMMON_H

#include <linux/of.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/arm-gic-common.h>

struct gic_quirk {
	const char *desc;
	const char *compatible;
	const char *property;
	bool (*init)(void *data);
	u32 iidr;
	u32 mask;
};

#ifdef CONFIG_RTOS_HAL_ITS_INIT_SUPPORT_RSV_MEM
struct of_resv {
	unsigned long pa_start;
	unsigned long pa_end;
};
#endif

#ifdef CONFIG_RTOS_HAL_SET_IRQPRIORITY
#define DEFAULT_PMR_VALUE	0xf0
#define LPI_PROP_PRIORITY_MASK	0xfc
#define MIN_IRQ_NUM		6
#define MIN_LPI_NUM		8192
#ifdef CONFIG_CORTEX_A15
#define MIN_IRQ_PRI_NUM		0xb0
#define MAX_IRQ_PRI_NUM		0xe0
#else
#define MIN_IRQ_PRI_NUM		0x60
#define MAX_IRQ_PRI_NUM		GICC_INT_PRI_THRESHOLD
#endif
#endif

int gic_configure_irq(unsigned int irq, unsigned int type,
                       void __iomem *base, void (*sync_access)(void));
void gic_dist_config(void __iomem *base, int gic_irqs,
		     void (*sync_access)(void));
void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void));
void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
		void *data);
void gic_enable_of_quirks(const struct device_node *np,
			  const struct gic_quirk *quirks, void *data);

void gic_set_kvm_info(const struct gic_kvm_info *info);

#ifdef CONFIG_RTOS_HAL_IRQ_BYPASS
extern struct mbigen_info mbigen_irq[HI1382_VIRQ_NUMS];
extern int irq_set_priority(unsigned int irq, const u8 prio);
#endif

#ifdef CONFIG_RTOS_HAL_DPE_IRQPRIO_DIVISION
void gic_irq_pri_init(void __iomem *base);
#endif

#ifdef CONFIG_RTOS_HAL_ITS_INIT_SUPPORT_RSV_MEM
extern struct of_resv its_gicr_rsv;
extern struct of_resv *gicr_resv;
struct of_resv *get_resv_mem(void);
struct page *alloc_rsv_pages(unsigned long size);
void its_of_mem_region(struct device_node *node,
				     struct of_resv **resv,
				     struct of_resv *resv_buf);
#endif

#endif /* _IRQ_GIC_COMMON_H */
